Experimenting with Emerging RISC-V Systems for Decentralised Machine Learning

TL;DR

This paper introduces a flexible framework for experimenting with decentralized machine learning on emerging RISC-V processors, including a new RISC-V port of PyTorch, and evaluates their performance and energy efficiency.

Contribution

It presents a domain-specific language and middleware for flexible DML experimentation across multiple architectures, including the first public RISC-V port of PyTorch.

Findings

Demonstrates the feasibility of running DML schemes on RISC-V processors.

Provides performance and energy efficiency benchmarks for RISC-V in DML tasks.

Introduces a portable RISC-V implementation of PyTorch for research and development.

Abstract

Decentralised Machine Learning (DML) enables collaborative machine learning without centralised input data. Federated Learning (FL) and Edge Inference are examples of DML. While tools for DML (especially FL) are starting to flourish, many are not flexible and portable enough to experiment with novel processors (e.g., RISC-V), non-fully connected network topologies, and asynchronous collaboration schemes. We overcome these limitations via a domain-specific language allowing us to map DML schemes to an underlying middleware, i.e. the FastFlow parallel programming library. We experiment with it by generating different working DML schemes on x86-64 and ARM platforms and an emerging RISC-V one. We characterise the performance and energy efficiency of the presented schemes and systems. As a byproduct, we introduce a RISC-V porting of the PyTorch framework, the first publicly available to our knowledge.