RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

TL;DR

This paper introduces RISE, a specialized RISC-V SoC designed to accelerate homomorphic encryption operations at the edge, significantly improving energy efficiency for message conversion, encryption, and decryption tasks.

Contribution

RISE provides an area and energy-efficient hardware solution that accelerates homomorphic encryption conversions and computations on edge devices, addressing a key bottleneck in privacy-preserving edge computing.

Findings

Up to 6191.19X more energy-efficient for message-to-ciphertext conversion.

Up to 2481.44X more energy-efficient for ciphertext-to-message conversion.

Effective acceleration of encryption and decryption operations using scalable parallelism.

Abstract

Today edge devices commonly connect to the cloud to use its storage and compute capabilities. This leads to security and privacy concerns about user data. Homomorphic Encryption (HE) is a promising solution to address the data privacy problem as it allows arbitrarily complex computations on encrypted data without ever needing to decrypt it. While there has been a lot of work on accelerating HE computations in the cloud, little attention has been paid to the message-to-ciphertext and ciphertext-to-message conversion operations on the edge. In this work, we profile the edge-side conversion operations, and our analysis shows that during conversion error sampling, encryption, and decryption operations are the bottlenecks. To overcome these bottlenecks, we present RISE, an area and energy-efficient RISC-V SoC. RISE leverages an efficient and lightweight pseudo-random number generator core and combines it with fast sampling techniques to accelerate the error sampling operations. To accelerate the encryption and decryption operations, RISE uses scalable, data-level parallelism to implement the number theoretic transform operation, the main bottleneck within the encryption and decryption operations. In addition, RISE saves area by implementing a unified en/decryption datapath, and efficiently exploits techniques like memory reuse and data reordering to utilize a minimal amount of on-chip memory. We evaluate RISE using a complete RTL design containing a RISC-V processor interfaced with our accelerator. Our analysis reveals that for message-to-ciphertext conversion and ciphertext-to-message conversion, using RISE leads up to 6191.19X and 2481.44X more energy-efficient solution, respectively, than when using just the RISC-V processor.