Performance Analysis of a Repetition Cat Code Architecture: Computing 256-bit Elliptic Curve Logarithm in 9 Hours with 126133 Cat Qubits

TL;DR

This paper evaluates a cat qubit-based quantum architecture capable of computing a 256-bit elliptic curve logarithm in 9 hours, providing detailed implementation guidance for large-scale quantum computing using repetition codes and lattice surgery.

Contribution

It presents a detailed performance analysis of a cat qubit architecture implementing Shor's algorithm for elliptic curve logarithms, including gate implementation and resource estimation.

Findings

Computes 256-bit elliptic curve logarithm in 9 hours with 126,133 cat qubits.

Demonstrates feasibility of large-scale quantum computation with cat qubits and repetition codes.

Provides a detailed architecture and implementation plan for practical quantum algorithms.

Abstract

Cat qubits provide appealing building blocks for quantum computing. They exhibit a tunable noise bias yielding an exponential suppression of bit flips with the average photon number and a protection against the remaining phase errors can be ensured by a simple repetition code. We here quantify the cost of a repetition code and provide valuable guidance for the choice of a large scale architecture using cat qubits by realizing a performance analysis based on the computation of discrete logarithms on an elliptic curve with Shor's algorithm. By focusing on a 2D grid of cat qubits with neighboring connectivity, we propose to implement 2-qubit gates via lattice surgery and Toffoli gates with off-line fault-tolerant preparation of magic states through projective measurements and subsequent gate teleportations. All-to-all connectivity between logical qubits is ensured by routing qubits. Assuming a ratio between single- and two-photon losses of 1e-5 and a cycle time of 500 ns, we show concretely that such an architecture can compute a 256-bit elliptic curve logarithm in 9 h with 126133 cat qubits and on average 19 photons by cat state. We give the details of the realization of Shor's algorithm so that the proposed performance analysis can be easily reused to guide the choice of architecture for others platforms.