General Position Problem of Butterfly Networks
R. Prabha, S. Renukaa Devi, Paul Manuel

TL;DR
This paper investigates the maximum size of a set of vertices in butterfly networks where no three vertices lie on a shortest path, introducing a new technique using isometric cycle cover numbers to solve this open problem.
Contribution
The paper presents a novel approach employing isometric cycle cover numbers to determine the general position number in butterfly networks, addressing an open problem.
Findings
Established an upper bound for the general position number using isometric cycle cover.
Provided a new method applicable to networks where previous techniques failed.
Opened new research directions for solving general position problems in complex networks.
Abstract
A general position set S is a set S of vertices in G(V,E) such that no three vertices of S lie on a shortest path in G. Such a set of maximum size in G is called a gpset of G and its cardinality is called the gp-number of G denoted by gp(G). The authors who introduced the general position problem stated that the general position problem for butterfly networks was open. A well-known technique to solve the general position problem for a given network is to use its isometric path cover number as an upper bound. The general position problem for butterfly networks remained open because this technique is not applicable for butterfly networks. In this paper, we adopt a new technique which uses the isometric cycle cover number as its upper bound. This technique is interesting and useful because it opens new avenues to solve the general position problem for networks which do not have solutions…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAdvanced Optical Network Technologies · Interconnection Networks and Systems · VLSI and FPGA Design Techniques
