Relaxing Hardware Requirements for Surface Code Circuits using Time-dynamics

TL;DR

This paper introduces time-dynamic surface code circuits that are more hardware-friendly by embedding on hexagonal grids, using ISWAP gates, and allowing flexible qubit roles, all while maintaining similar logical performance.

Contribution

It presents novel, time-dynamic surface code circuits that relax hardware constraints by enabling flexible layouts and gate choices without sacrificing performance.

Findings

Circuits embed on hexagonal grids instead of square grids.

Use of ISWAP gates instead of CNOT or CZ gates.

Maintain logical performance with 25% of standard footprint.

Abstract

The typical time-independent view of quantum error correction (QEC) codes hides significant freedom in the decomposition into circuits that are executable on hardware. Using the concept of detecting regions, we design time-dynamic QEC circuits directly instead of designing static QEC codes to decompose into circuits. In particular, we improve on the standard circuit constructions for the surface code, presenting new circuits that can embed on a hexagonal grid instead of a square grid, that can use ISWAP gates instead of CNOT or CZ gates, that can exchange qubit data and measure roles, and that move logical patches around the physical qubit grid while executing. All these constructions use no additional entangling gate layers and display essentially the same logical performance, having teraquop footprints within 25% of the standard surface code circuit. We expect these circuits to be of great interest to quantum hardware engineers, because they achieve essentially the same logical performance as standard surface code circuits while relaxing demands on hardware.