Low-depth simulations of fermionic systems on square-grid quantum hardware

TL;DR

This paper introduces a new method for mapping fermionic systems onto square-grid quantum hardware, resulting in significantly lower circuit depths and gate counts, enabling more efficient quantum simulations of complex models.

Contribution

The authors develop a novel operator decomposition and circuit compression technique combined with optimized fermion-to-qubit mappings for low-depth quantum simulations.

Findings

Achieved up to 70% reduction in circuit depth compared to previous methods.

Significant decrease in two-qubit gate counts using the XYZ-formalism with DK mapping.

Effective even without native parameterized two-qubit gates.

Abstract

We present a general strategy for mapping fermionic systems to quantum hardware with square qubit connectivity which yields low-depth quantum circuits, counted in the number of native two-qubit fSIM gates. We achieve this by leveraging novel operator decomposition and circuit compression techniques paired with specifically chosen low-depth fermion-to-qubit mappings and allow for a high degree of gate cancellations and parallelism. Our mappings retain the flexibility to simultaneously optimize for qubit counts or qubit operator weights and can be used to investigate arbitrary fermionic lattice geometries. We showcase our approach by investigating the tight-binding model, the Fermi-Hubbard model as well as the multi-orbital Hubbard-Kanamori model. We report unprecedentedly low circuit depths per single Trotter layer with up to a $70 \%$ improvement upon previous state-of-the-art. Our compression technique also results in significant reduction of two-qubit gates. We find the lowest gate-counts when applying the XYZ-formalism to the DK mapping. Additionally, we show that our decomposition and compression formalism produces favourable circuits even when no native parameterized two-qubit gates are available.