An FPGA-based readout chip emulator for the CMS ETL detector upgrade
L. Zhang, C. Edwards, D. Gong, X. Huang, J. Lee, C. Liu, T. Liu, T., Liu, J. Olsen, Q. Sun, J. Wu, J. Ye, W Zhang
TL;DR
This paper introduces an FPGA-based emulator board that replicates the digital functions of CMS ETL detector readout chips, aiding in design verification and system development.
Contribution
The development of an FPGA emulator for CMS ETL readout chips, enabling efficient digital design testing and system integration.
Findings
Successful implementation of FPGA emulator based on ETROC design
Verification of firmware accuracy and functionality
Support for system development and testing processes
Abstract
We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.
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Taxonomy
TopicsParticle Detector Development and Performance · Particle physics theoretical and experimental studies · Parallel Computing and Optimization Techniques