Bayesian Inference on Binary Spiking Networks Leveraging Nanoscale Device Stochasticity

TL;DR

This paper presents a novel PCM-based hardware implementation of Bayesian Neural Networks with binary synapses, leveraging nanoscale device stochasticity for efficient sampling, achieving comparable accuracy with significant hardware savings.

Contribution

It introduces a new PCM-based architecture for BNNs that uses device stochasticity for sampling, reducing hardware complexity without sacrificing accuracy.

Findings

Achieves accuracy and calibration error comparable to 8-bit fixed-point implementation.

Projects over 9× reduction in core area transistor count.

Demonstrates effectiveness on Breast Cancer Dataset classification.

Abstract

Bayesian Neural Networks (BNNs) can overcome the problem of overconfidence that plagues traditional frequentist deep neural networks, and are hence considered to be a key enabler for reliable AI systems. However, conventional hardware realizations of BNNs are resource intensive, requiring the implementation of random number generators for synaptic sampling. Owing to their inherent stochasticity during programming and read operations, nanoscale memristive devices can be directly leveraged for sampling, without the need for additional hardware resources. In this paper, we introduce a novel Phase Change Memory (PCM)-based hardware implementation for BNNs with binary synapses. The proposed architecture consists of separate weight and noise planes, in which PCM cells are configured and operated to represent the nominal values of weights and to generate the required noise for sampling, respectively. Using experimentally observed PCM noise characteristics, for the exemplary Breast Cancer Dataset classification problem, we obtain hardware accuracy and expected calibration error matching that of an 8-bit fixed-point (FxP8) implementation, with projected savings of over 9$\times$ in terms of core area transistor count.