Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher

TL;DR

This paper introduces a novel data prefetcher called Transmuter for manycore reconfigurable architectures, significantly improving graph workload performance by adapting CPU prefetching techniques to the unique architecture constraints.

Contribution

The paper designs and evaluates a new data prefetcher tailored for MRAs, incorporating runtime reconfiguration and cache redesign to enhance graph analytics performance.

Findings

Achieves up to 2.72x speedup on graph workloads

Outperforms baseline without prefetcher by 1.27x on average

Demonstrates effective adaptation of CPU prefetching techniques to MRAs

Abstract

The irregular nature of memory accesses of graph workloads makes their performance poor on modern computing platforms. On manycore reconfigurable architectures (MRAs), in particular, even state-of-the-art graph prefetchers do not work well (only 3% speedup), since they are designed for traditional CPUs. This is because caches in MRAs are typically not large enough to host a large quantity of prefetched data, and many employs shared caches that such prefetchers simply do not support. This paper studies the design of a data prefetcher for an MRA called Transmuter. The prefetcher is built on top of Prodigy, the current best-performing data prefetcher for CPUs. The key design elements that adapt the prefetcher to the MRA include fused prefetcher status handling registers and a prefetch handshake protocol to support run-time reconfiguration, in addition, a redesign of the cache structure in Transmuter. An evaluation of popular graph workloads shows that synergistic integration of these architectures outperforms a baseline without prefetcher by 1.27x on average and by as much as 2.72x on some workloads.