20 ps Time Resolution with a Fully-Efficient Monolithic Silicon Pixel Detector without Internal Gain Layer

TL;DR

This paper presents a monolithic silicon pixel detector achieving 20 ps time resolution without internal gain, using a fully depleted sensor and fast electronics, suitable for high-precision timing applications.

Contribution

It introduces a novel monolithic silicon pixel detector with optimized timing performance and demonstrates 20 ps resolution without internal gain layers.

Findings

Achieved 20 ps time resolution in a monolithic silicon pixel detector.

Demonstrated 99.8% efficiency at 130 V bias voltage.

Validated performance through laboratory and testbeam measurements.

Abstract

A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 {\mu}m thick epilayer of 350 {\Omega}cm resistivity were used to produce a fully depleted sensor. Laboratory and testbeam measurements of the analog channels present in the pixel matrix show that the sensor has a 130 V wide bias-voltage operation plateau at which the efficiency is 99.8%. Although this prototype does not include an internal gain layer, the design optimised for timing of the sensor and the front-end electronics provides a time resolutions of 20 ps.