Parallel Matrix Multiplication Using Voltage Controlled Magnetic Anisotropy Domain Wall Logic

TL;DR

This paper presents a novel voltage-controlled magnetic anisotropy approach to enhance the reliability and scalability of domain wall-magnetic tunnel junction logic gates for high-parallelism, low-energy, radiation-hard matrix multiplication in extreme environments.

Contribution

It introduces VCMA-enhanced DW-MTJ logic gates supporting multiple fanouts and demonstrates a systolic array for matrix multiplication with competitive performance and improved reliability.

Findings

Achieved reliable domain wall localization using VCMA

Supported multiple fanouts without area penalty

Demonstrated high-parallelism systolic array with comparable efficiency to CMOS

Abstract

The domain wall-magnetic tunnel junction (DW-MTJ) is a versatile device that can simultaneously store data and perform computations. These three-terminal devices are promising for digital logic due to their nonvolatility, low-energy operation, and radiation hardness. Here, we augment the DW-MTJ logic gate with voltage controlled magnetic anisotropy (VCMA) to improve the reliability of logical concatenation in the presence of realistic process variations. VCMA creates potential wells that allow for reliable and repeatable localization of domain walls. The DW-MTJ logic gate supports different fanouts, allowing for multiple inputs and outputs for a single device without affecting area. We simulate a systolic array of DW-MTJ Multiply-Accumulate (MAC) units with 4-bit and 8-bit precision, which uses the nonvolatility of DW-MTJ logic gates to enable fine-grained pipelining and high parallelism. The DW-MTJ systolic array provides comparable throughput and efficiency to state-of-the-art CMOS systolic arrays while being radiation-hard. These results improve the feasibility of using domain wall-based processors, especially for extreme-environment applications such as space.