Hardware-Aware Automated Neural Minimization for Printed Multilayer Perceptrons

TL;DR

This paper explores neural minimization techniques combined with custom circuit design to significantly reduce the area of printed multilayer perceptron classifiers, enabling more efficient printed electronics with minimal accuracy loss.

Contribution

It introduces the first analysis of neural minimization impacts on printed ML circuits, demonstrating substantial area reduction with minimal accuracy compromise.

Findings

Up to 8x area reduction with 5% accuracy loss

Neural minimization techniques are effective for printed ML circuits

Custom circuit implementations enhance area efficiency

Abstract

The demand of many application domains for flexibility, stretchability, and porosity cannot be typically met by the silicon VLSI technologies. Printed Electronics (PE) has been introduced as a candidate solution that can satisfy those requirements and enable the integration of smart devices on consumer goods at ultra low-cost enabling also in situ and ondemand fabrication. However, the large features sizes in PE constraint those efforts and prohibit the design of complex ML circuits due to area and power limitations. Though, classification is mainly the core task in printed applications. In this work, we examine, for the first time, the impact of neural minimization techniques, in conjunction with bespoke circuit implementations, on the area-efficiency of printed Multilayer Perceptron classifiers. Results show that for up to 5% accuracy loss up to 8x area reduction can be achieved.