C-SAR: SAT Attack Resistant Logic Locking for RSFQ Circuits
Junyao Zhang, Paul Bogdan, Shahin Nazarian

TL;DR
C-SAR introduces a logic locking technique for superconducting RSFQ circuits that significantly increases resistance to SAT-based attacks, ensuring higher security without excessive complexity increase.
Contribution
This paper presents C-SAR, a novel security method for superconducting RSFQ circuits that enhances SAT attack resistance by expanding key search space and increasing attack complexity.
Findings
C-SAR exponentially increases attack cost with key bits.
C-SAR's complexity grows linearly with key bits.
Effective protection against advanced SAT attacks.
Abstract
Since the development of semiconductor technologies, exascale computing and its associated applications have required increasing degrees of efficiency. Semiconductor-transistor-based circuits (STbCs) have struggled in increasing the GHz frequency. Emerging as an alternative to STbC, the superconducting electrons (SCE) technology promises higher-speed clock frequencies at ultra-low power consumption. The rapid single flux quantum (RSFQ) circuits have a theoretical potential for three orders of magnitude reduction in power while operating at clock frequencies higher than 100 GHz. Although the security in semiconductor technology has been extensively researched and developed, the security design in the superconducting field requires field demands attention. In this paper, C-SAR is presented that aims to protect the superconducting circuit electronics from Boolean satisfiability (SAT) based…
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Taxonomy
TopicsCryptographic Implementations and Security · Physical Unclonable Functions (PUFs) and Hardware Security · Security and Verification in Computing
