A Digital Delay Model Supporting Large Adversarial Delay Variations

TL;DR

This paper introduces an extended digital delay model that accurately accounts for large adversarial delay variations caused by PVT fluctuations and aging, improving the reliability of digital timing analysis.

Contribution

It extends the existing $ta$-IDM to support significantly larger adversarial delay variations, covering realistic PVT and aging effects.

Findings

The extended $ta$-IDM can model large delay fluctuations.

It accurately predicts delays under PVT variations and aging.

The model maintains faithfulness despite increased adversarial variations.

Abstract

Dynamic digital timing analysis is a promising alternative to analog simulations for verifying particularly timing-critical parts of a circuit. A necessary prerequisite is a digital delay model, which allows to accurately predict the input-to-output delay of a given transition in the input signal(s) of a gate. Since all existing digital delay models for dynamic digital timing analysis are deterministic, however, they cannot cover delay fluctuations caused by PVT variations, aging and analog signal noise. The only exception known to us is the $\eta$-IDM introduced by F\"ugger et al. at DATE'18, which allows to add (very) small adversarially chosen delay variations to the deterministic involution delay model, without endangering its faithfulness. In this paper, we show that it is possible to extend the range of allowed delay variations so significantly that realistic PVT variations and aging are covered by the resulting extended $\eta$-IDM.