RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices

TL;DR

RAD-Sim is a cycle-level simulator designed to enable rapid, application-driven exploration of the complex design space of novel reconfigurable acceleration devices that integrate FPGA fabrics, specialized accelerators, and NoC communication.

Contribution

This work introduces RAD-Sim, a new simulation tool that facilitates efficient exploration and analysis of RAD architectures, addressing the lack of suitable tools for complex design interactions.

Findings

RAD-Sim enables rapid simulation of RAD architectures.

It helps quantify the impact of design choices on performance.

Demonstrated with a deep learning inference overlay.

Abstract

With the continued growth in field-programmable gate array (FPGA) capacity and their incorporation into new environments such as datacenters, we have witnessed the introduction of a new class of reconfigurable acceleration devices (RADs) that go beyond conventional FPGA architectures. These devices combine a reconfigurable fabric with coarse-grained domain-specialized accelerator blocks all connected via a high-performance packet-switched network-on-chip (NoC) for efficient system-wide communication. However, we lack the tools necessary to efficiently explore the huge design space for RADs, study the complex interactions between their different components and evaluate various combinations of design choices. In this work, we develop RAD-Sim, a cycle-level architecture simulator that allows rapid application-driven exploration of the design space of novel RADs. To showcase the capabilities of RADSim, we map and simulate a state-of-the-art deep learning (DL) inference overlay on a RAD instance incorporating an FPGA fabric and a complex of hard matrix-vector multiplication engines, communicating over a system-wide NoC. Through this example, we show how RAD-Sim can help architects quantify the effect of changing specific architecture parameters on end-to-end application performance.