Lower-temperature fabrication of airbridges by grayscale lithography to increase yield of nanowire transmons in circuit QED quantum processors

TL;DR

This paper introduces a grayscale lithography technique to fabricate airbridges at lower temperatures, significantly increasing the yield of nanowire transmons in circuit QED quantum processors by reducing thermal stress on superconducting components.

Contribution

It demonstrates a novel low-temperature fabrication method for airbridges using grayscale lithography, improving yield in superconducting nanowire transmon qubits.

Findings

Lower fabrication temperature from 200°C to 150°C.

Significant increase in transmon qubit yield.

Reduced thermal impact on Josephson elements.

Abstract

Quantum hardware based on circuit quantum electrodynamics makes extensive use of airbridges to suppress unwanted modes of wave propagation in coplanar-waveguide transmission lines. Airbridges also provide an interconnect enabling transmission lines to cross. Traditional airbridge fabrication produces a curved profile by reflowing resist at elevated temperature prior to metallization. The elevated temperature can affect the coupling energy and even yield of pre-fabricated Josephson elements of superconducting qubits, tuneable couplers and resonators. We employ grayscale lithography in place of reflow to reduce the peak airbridge processing temperature from $200$ to $150^\circ\mathrm{C}$, showing a substantial yield increase of transmon qubits with Josephson elements realized using Al-contacted InAs nanowires.