Duet: Creating Harmony between Processors and Embedded FPGAs
Ang Li, August Ning, David Wentzlaff

TL;DR
Duet introduces a scalable manycore-FPGA architecture that enables embedded FPGAs to operate as equal peers with processors, enhancing fine-grained acceleration and hardware augmentation for improved performance.
Contribution
It presents a novel non-intrusive, cache-coherent integration of embedded FPGAs with processors, enabling full potential utilization through post-fabrication enhancements.
Findings
Processor-accelerator communication latency reduced by up to 82%
Bandwidth increased by up to 9.5x
Achieved 1.5-24.9x speedup on application benchmarks
Abstract
The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained acceleration opportunities available in broader domains and squanders host processors' compute power. This paper presents Duet, a scalable, manycore-FPGA architecture that promotes embedded FPGAs (eFPGA) to be equal peers with processors through non-intrusive, bi-directionally cache-coherent integration. In contrast to existing CPU-FPGA hybrid systems in which the processors play a supportive role, Duet unleashes the full potential of both the processors and the eFPGAs with two classes of post-fabrication enhancements: fine-grained acceleration, which partitions an application into small tasks and offloads the frequently-invoked, compute-intensive ones onto various small accelerators, leveraging the processors…
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