Fast and energy-efficient derivatives risk analysis: Streaming option Greeks on Xilinx and Intel FPGAs
Mark Klaisoongnoen, Nick Brown, Oliver Brown

TL;DR
This paper demonstrates that FPGA-based acceleration of derivatives risk analysis significantly outperforms CPU and GPU implementations, achieving up to 8.2 times faster performance and 9 times lower energy consumption by porting and optimizing across different FPGA architectures.
Contribution
The paper introduces a host-data-streaming approach for FPGA acceleration of derivatives risk analysis, outperforming previous implementations and exploring cross-architecture porting techniques.
Findings
Up to 4.6x performance improvement on Xilinx FPGA
Up to 8.2x speedup over CPU and GPU
9x reduction in energy consumption
Abstract
Whilst FPGAs have enjoyed success in accelerating high-frequency financial workloads for some time, their use for quantitative finance, which is the use of mathematical models to analyse financial markets and securities, has been far more limited to-date. Currently, CPUs are the most common architecture for such workloads, and an important question is whether FPGAs can ameliorate some of the bottlenecks encountered on those architectures. In this paper we extend our previous work accelerating the industry standard Securities Technology Analysis Center's (STAC\textregistered) derivatives risk analysis benchmark STAC-A2\texttrademark{}, by first porting this from our previous Xilinx implementation to an Intel Stratix-10 FPGA, exploring the challenges encountered when moving from one FPGA architecture to another and suitability of techniques. We then present a host-data-streaming approach…
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