Quantum chip design optimization and automation in superconducting coupler architecture

TL;DR

This paper introduces a new method for designing superconducting qubit-coupler architectures, identifying key conditions and bounds for optimal layout, and demonstrating an effective automated design procedure with state-of-the-art results.

Contribution

It provides the first zero-coupling condition based on layout geometry, derives an upper bound for qubit-qubit coupling, and proposes an automated layout optimization method.

Findings

Zero-coupling condition depends only on layout geometry.

Upper bound of coupling is independent of specific layouts.

Automated design procedure achieves high-performance layouts, including a 3202 um long-range QCQ.

Abstract

Superconducting coupler architecture demonstrates great potential for scalable and high-performance quantum processors, yet how to design efficiently and automatically 'Qubit-Coupler-Qubit (QCQ)' of high performance from the layout perspective remains obscure. In this work, this issue is studied for the first time resulting in three key findings. Firstly, we acquire the crucial zero-coupling condition that is only dependent on the geometric design of the layout. Secondly, the upper bound of the qubit-qubit effective coupling is found as $0.0822~ \omega_l/\beta_s^2$ which surprisingly depends only on the artificially pre-decided quantities $\omega_l, \beta_s$ instead of specific layouts. Thirdly, we propose an optimal layout design procedure to reach the very upper bound, leading to efficient and high-performance layout design. The effectiveness of the procedure has been demonstrated scrupulously using electromagnetic simulation experiments. As a stirring application, we report a state-of-the-art 3202 um long-range and scalable QCQ layout that is especially crucial to quantum error correction. Our work provides practical guides to optimize the performance of the existing coupler architecture, find out novel layouts, and further advance the progress of quantum chip design automation.