BioSFQ circuit family for neuromorphic computing: Bridging digital and analog domains of superconductor technologies

TL;DR

This paper introduces bioSFQ circuits for neuromorphic computing that leverage superconductor SFQ technology, enabling high-speed, low-energy analog bipolar operations with inherent asynchrony and collision tolerance, demonstrated through fabrication and testing.

Contribution

The paper presents a novel bioSFQ circuit family with bipolar transfer capabilities, including a new comparator and multiplier, advancing superconducting neuromorphic computing.

Findings

Developed a dual-rail comparator for bipolar signals

Fabricated and tested bioSFQ circuits in a multi-layer niobium process

Demonstrated asynchronous operation with collision tolerance

Abstract

Superconductor single flux quantum (SFQ) technology is attractive for neuromorphic computing due to low energy dissipation and high, potentially up to 100 GHz, clock rates. We have recently suggested a new family of bioSFQ circuits (V.K. Semenov et al., IEEE TAS, vol. 32, no. 4, 1400105, 2022) where information is stored as a value of current in a superconducting loop and transferred as a rate of SFQ pulses propagating between the loops. This approach, in the simplest case dealing with positive numbers, requires single-line transfer channels. In the more general case of bipolar numbers, it requires dual-rail transfer channels. To address this need, we have developed a new comparator with a dual-rail output. This comparator is an essential part of a bipolar multiplier that has been designed, fabricated, and tested. We discuss bioSFQ circuits for implementing an analog bipolar divide operation $Y/X$ and a square root operation $X^{1/2}$. We discuss strategic advantages of the suggested bioSFQ approach, e.g., an inherently asynchronous character of bioSFQ cells which do not require explicit clock signals. As a result, bioSFQ circuits are free of racing errors and tolerant to occasional collision of propagating SFQ pulses. This tolerance is due to stochastic nature of data signals generated by comparators operating within their gray zone. The circuits were fabricated in the eight-niobium-layer fabrication process SFQ5ee developed for superconductor electronics at MIT Lincoln Laboratory.