Approximate Scan Flip-flop to Reduce Functional Path Delay and Power Consumption

TL;DR

This paper proposes two new scan flip-flop designs using 10nm FinFET technology to reduce delay and power consumption caused by multiplexers in scan chains, improving performance for high-performance designs.

Contribution

Introduction of two novel scan flip-flop designs that mitigate mux-induced delay and power issues in scan chains at advanced technology nodes.

Findings

Significant reduction in functional path delay.

Notable decrease in test power consumption.

Validated performance improvements through experiments.

Abstract

The scan-based testing has been widely used as a Design-for-Test (DfT) mechanism for most recent designs. It has gained importance not only in manufacturing testing but also in online testing and debugging. However, the multiplexer-based scan flip-flop, which is the basic building block of scan chain, is troubled with a set of issues such as mux-induced additional delay and test power among others. The effect of additional delay due to the multiplexer on the functional path (D in path) has started influencing the clock period, particularly at the lower technology nodes for the high-performance design. In this work, we propose two scan flip-flop designs using 10nm FinFET technology to address the problem of mux-induced delay and internal power. The proposed designs have been experimentally validated for performance gain and power reduction and compared to the existing designs.