Multipartite High-dimensional Quantum State Engineering via Discrete Time Quantum Walk

TL;DR

This paper introduces two novel schemes for engineering arbitrary multipartite high-dimensional quantum states using discrete-time quantum walks, enabling efficient state preparation and reducing communication costs.

Contribution

It presents two new quantum walk-based schemes for arbitrary quantum state engineering in multipartite high-dimensional systems, with improved efficiency and applicability.

Findings

Demonstrated schemes for preparing generalized Bell states.

Showed reduction in quantum communication costs for distant particles.

Designed circuits matching current best results in size and depth.

Abstract

Quantum state engineering, namely the generation and control of arbitrary quantum states, is drawing more and more attention due to its wide applications in quantum information and computation. However, there is no general method in theory, and the existing schemes also depend heavily on the selected experimental platform. In this manuscript, we give two schemes for the engineering task of arbitrary quantum state in $c$-partite $d$-dimensional system, both of which are based on discrete-time quantum walk with a $2^c$-dimensional time- and position-dependent coin. The first procedure is a $d$-step quantum walk where all the $d$ coins are non-identity, while the second procedure is an $O(d)$-step quantum walk where only $O(\log d)$ coins are non-identity. A concrete example of preparing generalized Bell states is given to demonstrate the first scheme we proposed. We also show how these schemes can be used to reduce the cost of long-distance quantum communication when the particles involved in the system are far away from each other. Furthermore, the first scheme can be applied to give an alternative approach to the quantum state preparation problem which is one of the fundamental tasks of quantum information processing. We design circuits for quantum state preparation with the help of our quantum state engineering scheme that match the best current result in both size and depth of the circuit asymptotically.