A Toolchain for Streaming Dataflow Accelerator Designs for Big Data Analytics: Defining an IR for Composable Typed Streaming Dataflow Designs

TL;DR

This paper introduces Tydi, an open specification for streaming dataflow in digital circuits, and presents an open-source IR that enables high-level, reusable, and verifiable component interfaces for big data analytics hardware design.

Contribution

The paper develops an open-source IR for Tydi's data-centric streaming interfaces, supporting reuse, verification, and integration with hardware design tools.

Findings

IR supports component reuse across projects

IR enables high-level interface verification

Backend targeting VHDL demonstrates practical applicability

Abstract

Tydi is an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. This provides a higher-level method for defining interfaces between components as opposed to existing bit- and byte-based interface specifications. In this thesis, an open-source intermediate representation (IR) is introduced which allows for the declaration of Tydi's types. The IR enables creating and connecting components with Tydi Streams as interfaces, called Streamlets. It also lets backends for synthesis and simulation retain high-level information, such as documentation. Types and Streamlets can be easily reused between multiple projects, and Tydi's streams and type hierarchy can be used to define interface contracts, which aid collaboration when designing a larger system. The IR codifies the rules and properties established in the Tydi specification and serves to complement computation-oriented hardware design tools with a data-centric view on interfaces. To support different backends and targets, the IR is focused on expressing interfaces, and complements behavior described by hardware description languages and other IRs. Additionally, a testing syntax for the verification of inputs and outputs against abstract streams of data, and for substituting interdependent components, is presented which allows for the specification of behavior. To demonstrate this IR, a grammar, parser, and query system have been created, and paired with a backend targeting VHDL.