Tydi-lang: a language for typed streaming hardware -- A manual for future Tydi-lang compiler developers

TL;DR

Tydi-lang is a high-level hardware description language that leverages the Tydi specification to simplify streaming hardware design, improve collaboration, and reduce development effort through an open-source compiler and simulation tools.

Contribution

It introduces Tydi-lang, a new HDL that incorporates Tydi-spec for typed streams, along with a compiler and simulation blueprint to enhance hardware design abstraction.

Findings

Successfully translates SQL to VHDL using Tydi-lang

Reduces design effort and improves abstraction in streaming hardware

Provides an open-source compiler and simulation tools

Abstract

Transferring composite data structures with variable-length fields often requires designing non-trivial protocols that are not compatible between hardware designs. When each project designs its own data format and protocols the ability to collaborate between hardware developers is diminished, which is an issue especially in the open-source community. Because the high-level meaning of a protocol is often lost in translation to low-level languages when a custom protocol needs to be designed, extra documentation is required, the interpretation of which introduces new opportunities for errors. The Tydi specification (Tydi-spec) was proposed to address the above issues by codifying the composite and variable-length data structures in a type and providing a standard protocol to transfer typed data among hardware components. The Tydi intermediate representation (Tydi-IR) extends the Tydi-spec by defining typed interfaces, typed components, and connections among typed components. In this thesis, we propose Tydi-lang, a high-level hardware description language (HDL) for streaming designs. The language incorporates Tydi-spec to describe typed streams and provides templates to describe abstract reusable components. We also implement an open-source compiler from Tydi-lang to Tydi-IR. We leverage a Tydi-IR to VHDL compiler, and also present a simulator blueprint to identify streaming bottlenecks. We show several Tydi-lang examples to translate high-level SQL to VHDL to demonstrate that Tydi-lang can efficiently raise the level of abstraction and reduce design effort.