A Soft SIMD Based Energy Efficient Computing Microarchitecture

TL;DR

This paper introduces a flexible, energy-efficient microarchitecture with a two-stage SIMD pipeline that dynamically supports operand quantization and zero-skipping, significantly reducing area and energy consumption for machine learning computations.

Contribution

It presents a novel microarchitecture enabling dynamic sub-word bitwidth adjustment and efficient SIMD operations, improving energy and area efficiency over traditional hardware SIMD solutions.

Findings

Up to 53.1% smaller area than traditional SIMD hardware

Performs multiplication up to 88.8% more efficiently

Supports fine-grained operand quantization dynamically

Abstract

The ever-increasing size and computational complexity of today's machine-learning algorithms pose an increasing strain on the underlying hardware. In this light, novel and dedicated architectural solutions are required to optimize energy efficiency by leveraging opportunities (such as intrinsic parallelism and robustness to quantization errors) exposed by algorithms. We herein address this challenge by introducing a flexible two-stages computing pipeline. The pipeline can support fine-grained operand quantization through software-supported Single Instruction Multiple Data (SIMD) operations. Moreover, it can efficiently execute sequential multiplications over SIMD sub-words thanks to zero-skipping and Canonical Signed Digit (CSD) coding. Finally, a lightweight repacking unit allows changing the bitwidth of sub-words at run-time dynamically. These features are implemented within a tight energy and area budget. Indeed, experimental results showcase that our approach greatly outperforms traditional hardware SIMD ones both in terms of area and energy requirements. In particular, our pipeline occupies up to 53.1% smaller than a hardware SIMD one supporting the same sub-word widths, while performing multiplication up to 88.8% more efficiently.