On BTI Aging Rejuvenation in Memory Address Decoders

TL;DR

This paper introduces a low-cost rejuvenation scheme for memory address decoders that mitigates BTI aging effects, extending memory lifetime with minimal overhead by applying periodic auxiliary workloads.

Contribution

The paper presents a novel, practical aging mitigation method using rejuvenation workloads to counteract BTI effects in memory decoders, applicable to existing hardware.

Findings

Multiple-times lifetime extension achieved

Negligible execution overhead

Effective mitigation of BTI aging effects

Abstract

Memory designs require timing margins to compensate for aging and fabrication process variations. With technology downscaling, aging mechanisms became more apparent, and larger margins are considered necessary. This, in return, means a larger area requirement and lower performance for the memory. Bias Temperature Instability (BTI) is one of the main contributors to aging, which slows down transistors and ultimately causes permanent faults. In this paper, first, we propose a low-cost aging mitigation scheme, which can be applied to existing hardware to mitigate aging on memory address decoder logic. We mitigate the BTI effect on critical transistors by applying a rejuvenation workload to the memory. Such an auxiliary workload is executed periodically to rejuvenate transistors that are located on critical paths of the address decoder. Second, we analyze workloads' efficiency to optimize the mitigation scheme. Experimental results performed with realistic benchmarks demonstrate several-times lifetime extension with a negligible execution overhead.