Enabling the Reflex Plane with the nanoPU
Stephen Ibanez, Alex Mallery, Serhat Arslan, Theo Jepsen, Muhammad, Shahbaz, Changhoon Kim, and Nick McKeown

TL;DR
This paper introduces the nanoPU, a new type of CPU designed for high-speed network processing, demonstrating its effectiveness through benchmarking network services and proposing a reflex plane for rapid telemetry and control.
Contribution
The paper presents the nanoPU, a novel CPU architecture that enables microsecond-scale network processing, with prototype implementations and performance evaluations of key network services.
Findings
Packet classification is 2× faster on nanoPU.
Telemetry report processing is over 10× faster.
Raft consensus runs in 3 μs, twice as fast as prior approaches.
Abstract
Many recent papers have demonstrated fast in-network computation using programmable switches, running many orders of magnitude faster than CPUs. The main limitation of writing software for switches is the constrained programming model and limited state. In this paper we explore whether a new type of CPU, called the nanoPU, offers a useful middle ground, with a familiar C/C++ programming model, and potentially many terabits/second of packet processing on a single chip, with an RPC response time less than 1 s. To evaluate the nanoPU, we prototype and benchmark three common network services: packet classification, network telemetry report processing, and consensus protocols on the nanoPU. Each service is evaluated using cycle-accurate simulations on FPGAs in AWS. We found that packets are classified 2 faster and INT reports are processed more than an order of magnitude quickly…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsInterconnection Networks and Systems · Software-Defined Networks and 5G · Advanced Memory and Neural Computing
