Interaction graph-based characterization of quantum benchmarks for improving quantum circuit mapping techniques

TL;DR

This paper introduces a novel approach using interaction graph properties to analyze quantum circuits, enhancing understanding of hardware constraints and improving circuit mapping techniques for quantum processors.

Contribution

It extends quantum circuit characterization by incorporating graph theory metrics, enabling better analysis, clustering, and comparison of circuits across different quantum hardware.

Findings

Correlation between interaction graph parameters and mapping performance.

Enhanced analysis and clustering of quantum circuits.

Benchmark dataset for future quantum compilation research.

Abstract

To execute quantum circuits on a quantum processor, they must be modified to meet the physical constraints of the quantum device. This process, called quantum circuit mapping, results in a gate/circuit depth overhead that depends on both the circuit properties and the hardware constraints, being the limited qubit connectivity a crucial restriction. In this paper, we propose to extend the characterization of quantum circuits by including qubit interaction graph properties using graph theory-based metrics in addition to previously used circuit-describing parameters. This approach allows for in-depth analysis and clustering of quantum circuits and a comparison of performance when run on different quantum processors, aiding in developing better mapping techniques. Our study reveals a correlation between interaction graph-based parameters and mapping performance metrics for various existing configurations of quantum devices. We also provide a comprehensive collection of quantum circuits and algorithms for benchmarking future compilation techniques and quantum devices.