Threshold voltage instability by charge trapping effects in the gate region of p-GaN HEMTs

TL;DR

This study investigates the threshold voltage instability in p-GaN HEMTs caused by charge trapping at interfaces, revealing how bias stress and temperature influence trap dynamics and device stability.

Contribution

It provides new insights into charge trapping mechanisms, trap activation energies, and the formation of dislocation-like defects affecting p-GaN HEMT performance.

Findings

Charge trapping causes threshold voltage shifts depending on bias polarity.

Activation energies for electron and hole traps are identified and linked to vacancies.

Long-term bias stress induces dislocation-like defects creating new electron traps.

Abstract

In this work, the threshold voltage instability of normally-off p-GaN high electron mobility transistors (HEMTs) has been investigated by monitoring the gate current density during device on-state. The origin of the gate current variations under stress has been ascribed to charge trapping occurring at the different interfaces in the metal/p-GaN/AlGaN/GaN system. In particular, depending on the stress bias level, electrons (VG < 6 V) or holes (VG > 6 V) are trapped, causing a positive or negative threshold voltage shift {DVTH, respectively. By monitoring the gate current variations at different temperatures, the activation energies associated to the electrons and holes trapping could be determined and correlated with the presence of nitrogen (electron traps) or gallium (hole traps) vacancies. Moreover, the electrical measurements suggested the generation of a new electron-trap upon long-time bias stress, associated to the creation of crystallographic dislocation-like defects extending across the different interfaces (p-GaN/AlGaN/GaN) of the gate stack.