Non-Linear Analog Processing in MIMO Systems with Coarse Quantization

TL;DR

This paper explores the use of nonlinear analog operators before sampling in MIMO systems with coarse quantization to improve achievable rates and reduce power consumption, supported by circuit simulations and measurements.

Contribution

It introduces a novel receiver architecture combining nonlinear analog processing with few-bit ADCs, demonstrating potential rate improvements and power efficiency gains.

Findings

Nonlinear analog operators can mitigate rate loss in coarse quantization.

Proposed architectures show improved power efficiency in simulations.

Experimental results validate the practical feasibility of the approach.

Abstract

Analog to digital converters (ADCs) are a major contributor to the power consumption of multiple-input multiple-output (MIMO) receivers in large bandwidth millimeter-wave systems. Prior works have considered two mitigating solutions to reduce the ADC power consumption: i) decreasing the number of ADCs via analog and hybrid beamforming, and ii) decreasing the ADC resolution, i.e., utilizing one-bit and few-bit ADCs. These mitigating solutions lead to performance loss in terms of achievable rates due to increased quantization error. In this work, the use of nonlinear analog operators such as envelope detectors and polynomial operators, prior to sampling and quantization is considered, as a way to reduce the aforementioned rate-loss. The receiver architecture consists of linear combiners, nonlinear analog operators, and few-bit ADCs. The fundamental performance limits of the resulting communication system, in terms of achievable rates, are investigated under various assumptions on the set of implementable analog operators. Extensive numerical evaluations are provided to evaluate the set of achievable rates and the power consumption of the proposed receiver architectures. Circuit simulations and measurement results, based on both 22 nm FDSOI CMOS technology and 65 nm Bulk CMOS transistor technologies, are provided to justify the power efficiency of the proposed receiver architectures.