Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs

TL;DR

This paper presents a comprehensive workflow for automating task modules partitioning, scheduling, and floorplanning in partially dynamically reconfigurable FPGAs with heterogeneous resources, improving performance and resource reuse.

Contribution

It introduces a complete automation workflow for FPGA-PDRS, including pre-processing, exploration, and post-optimization, addressing gaps in existing methods.

Findings

Performance improved by 18.7% compared to state-of-the-art

Communication cost reduced by 8.6% on average

Post-optimization increases floorplan success rate by 14%

Abstract

Modern field programmable gate array(FPGA) can be partially dynamically reconfigurable with heterogeneous resources distributed on the chip. And FPGA-based partially dynamically reconfigurable system(FPGA-PDRS) can be used to accelerate computing and improve computing flexibility. However, the traditional design of FPGA-PDRS is based on manual design. Implementing the automation of FPGA-PDRS needs to solve the problems of task modules partitioning, scheduling, and floorplanning on heterogeneous resources. Existing works only partly solve problems for the automation process of FPGA-PDRS or model homogeneous resource for FPGA-PDRS. To better solve the problems in the automation process of FPGA-PDRS and narrow the gap between algorithm and application, in this paper, we propose a complete workflow including three parts, pre-processing to generate the list of task modules candidate shapes according to the resources requirements, exploration process to search the solution of task modules partitioning, scheduling, and floorplanning, and post-optimization to improve the success rate of floorplan. Experimental results show that, compared with state-of-the-art work, the proposed complete workflow can improve performance by 18.7\%, reduce communication cost by 8.6\%, on average, with improving the resources reuse rate of the heterogeneous resources on the chip. And based on the solution generated by the exploration process, the post-optimization can improve the success rate of the floorplan by 14\%.