Eliminating Leakage in Volatile Memory with Anti-Ferroelectric Transistors

TL;DR

This paper introduces a novel volatile memory technology using anti-ferroelectric transistors that achieves leakage-free, refresh-free data retention with high endurance and long retention time, improving the balance of density, power, and reliability.

Contribution

It demonstrates a new leakage-free volatile memory concept with anti-ferroelectric transistors, surpassing limitations of existing volatile and nonvolatile memories.

Findings

Leakage-free and refresh-free memory achieved with AFeFETs

Endurance of about 10^12 cycles demonstrated

Retention time exceeds 10 years

Abstract

Cache serves as a temporary data memory module in many general-purpose processors and domain-specific accelerators. Its density, power, speed, and reliability play a critical role in enhancing the overall system performance and quality of service. Conventional volatile memories, including static random-access memory (SRAM) and embedded dynamic random-access memory (eDRAM) in the complementary metal-oxide-semiconductor technology, have high performance and good reliability. However, the inherent leakage in both SRAM and eDRAM hinders further improvement towards smaller feature sizes and higher energy efficiency. Although the emerging nonvolatile memories can eliminate the leakage efficiently, the penalties of lower speed and degraded reliability are significant. This article reveals a new opportunity towards leakage-free volatile static memory beyond the known paradigms of existing volatile and nonvolatile memories. By engineering a double-well energy landscape with the assistance of a clamping voltage bias, leakage-free and refresh-free state retention of volatile memory is achieved for the first time. This new memory is highlighted by both the ultra-low leakage of nonvolatile memories and the speed, energy, and reliability advantages of volatile memories. A proof-of-concept memory is demonstrated using in-house anti-ferroelectric field-effect transistors (AFeFETs), delivering an extrapolated endurance of about 1012 cycles, a retention time of over 10 years, and no subthreshold channel leakage current. Such a new concept of AFeFET-based memory enables an improved balance between density, power, and reliability beyond all existing memory solutions.