A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface

TL;DR

This paper introduces a high-throughput SRAM-based charge-domain computing-in-memory macro that performs parallel multiply-accumulate and ReLU operations on 8-bit vectors, significantly improving speed and energy efficiency for data-intensive tasks.

Contribution

It presents a novel SRAM-based charge-domain CiM macro capable of completing MAC and ReLU operations on 8-bit vectors in one cycle with high throughput and efficiency, addressing scaling challenges.

Findings

Achieves 51.2 GOPS throughput and 10.3 TOPS/W energy efficiency.

Completes MAC and ReLU of two 8-bit vectors in one cycle.

Maintains 88.6% accuracy on CIFAR-10 dataset.

Abstract

Performing data-intensive tasks in the von Neumann architecture is challenging to achieve both high performance and power efficiency due to the memory wall bottleneck. Computing-in-memory (CiM) is a promising mitigation approach by enabling parallel in-situ multiply-accumulate (MAC) operations within the memory with support from the peripheral interface and datapath. SRAM-based charge-domain CiM (CD-CiM) has shown its potential of enhanced power efficiency and computing accuracy. However, existing SRAM-based CD-CiM faces scaling challenges to meet the throughput requirement of high-performance multi-bit-quantization applications. This paper presents an SRAM-based high-throughput ReLU-optimized CD-CiM macro. It is capable of completing MAC and ReLU of two signed 8b vectors in one CiM cycle with only one A/D conversion. Along with non-linearity compensation for the analog computing and A/D conversion interfaces, this work achieves 51.2GOPS throughput and 10.3TOPS/W energy efficiency, while showing 88.6% accuracy in the CIFAR-10 dataset.