FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training

TL;DR

This paper presents an FPGA-based adaptive machine learning equalizer capable of real-time channel impairment compensation through on-chip training using gradient backpropagation.

Contribution

It introduces a novel FPGA implementation of a multi-layer machine learning equalizer with integrated on-chip training for real-time adaptation.

Findings

Successful real-time adaptation to channel impairments

Efficient FPGA implementation of multi-layer equalizer

On-chip training enables dynamic channel compensation

Abstract

We design and implement an adaptive machine learning equalizer that alternates multiple linear and nonlinear computational layers on an FPGA. On-chip training via gradient backpropagation is shown to allow for real-time adaptation to time-varying channel impairments.