Low-Resolution Horizontal and Vertical Layered Mutual Information Maximizing LDPC Decoding

TL;DR

This paper compares horizontal and vertical layered schedules in low-resolution LDPC decoding, highlighting hardware efficiency and similar error performance, with a slight advantage in iteration count for horizontal scheduling.

Contribution

It introduces a comparison of two layered scheduling variants combined with mutual information maximizing compression in low-resolution LDPC decoding.

Findings

Similar error rate performance for both schedules

Horizontal schedule achieves slightly fewer iterations

Most hardware complexity resides in routing network operations

Abstract

We investigate iterative low-resolution message-passing algorithms for quasi-cyclic LDPC codes with horizontal and vertical layered schedules. Coarse quantization and layered scheduling are highly relevant for hardware implementations to reduce the bit width of messages and the number of decoding iterations. As a novelty, this paper compares the two scheduling variants in combination with mutual information maximizing compression operations in variable and check nodes. We evaluate the complexity and error rate performance for various configurations. Dedicated hardware architectures for regular quasi-cyclic LDPC decoders are derived on a conceptual level. The hardware-resource estimates confirm that most of the complexity lies within the routing network operations. Our simulations reveal similar error rate performance for both layered schedules but a slightly lower average iteration count for the horizontal decoder.