THOR -- A Neuromorphic Processor with 7.29G TSOP$^2$/mm$^2$Js Energy-Throughput Efficiency

TL;DR

THOR is an all-digital neuromorphic processor designed with a novel memory hierarchy and neuron update architecture, achieving a 3X improvement in energy-throughput efficiency over previous digital neuromorphic hardware.

Contribution

The paper introduces THOR, a new digital neuromorphic processor with innovative architecture that significantly enhances energy-throughput efficiency for edge computing applications.

Findings

Achieves 7.29G TSOP^2/mm^2Js ET efficiency at 0.9V, 400 MHz.

Demonstrates a 3X improvement over existing digital neuromorphic processors.

Implemented in 28nm FDSOI CMOS technology with post-layout results.

Abstract

Neuromorphic computing using biologically inspired Spiking Neural Networks (SNNs) is a promising solution to meet Energy-Throughput (ET) efficiency needed for edge computing devices. Neuromorphic hardware architectures that emulate SNNs in analog/mixed-signal domains have been proposed to achieve order-of-magnitude higher energy efficiency than all-digital architectures, however at the expense of limited scalability, susceptibility to noise, complex verification, and poor flexibility. On the other hand, state-of-the-art digital neuromorphic architectures focus either on achieving high energy efficiency (Joules/synaptic operation (SOP)) or throughput efficiency (SOPs/second/area), resulting in poor ET efficiency. In this work, we present THOR, an all-digital neuromorphic processor with a novel memory hierarchy and neuron update architecture that addresses both energy consumption and throughput bottlenecks. We implemented THOR in 28nm FDSOI CMOS technology and our post-layout results demonstrate an ET efficiency of 7.29G $\text{TSOP}^2/\text{mm}^2\text{Js}$ at 0.9V, 400 MHz, which represents a 3X improvement over state-of-the-art digital neuromorphic processors.