Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays

TL;DR

Canal is a flexible, Python-based tool that simplifies the design and exploration of reconfigurable interconnects for CGRAs, improving efficiency and adaptability for various applications.

Contribution

Introduces Canal, a novel Python-embedded DSL and compiler that enables rapid generation and exploration of CGRA interconnect architectures using a graph-based IR.

Findings

Able to generate both static and hybrid interconnects

Facilitates fast design space exploration

Supports modification of switch box topology and routing parameters

Abstract

The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored to maintain efficiency and performance across a variety of evolving applications. This paper presents Canal, a Python-embedded domain-specific language (eDSL) and compiler for specifying and generating reconfigurable interconnects for CGRAs. Canal uses a graph-based intermediate representation (IR) that allows for easy hardware generation and tight integration with place and route tools. We evaluate Canal by constructing both a fully static interconnect and a hybrid interconnect with ready-valid signaling, and by conducting design space exploration of the interconnect architecture by modifying the switch box topology, the number of routing tracks, and the interconnect tile connections. Through the use of a graph-based IR for CGRA interconnects, the eDSL, and the interconnect generation system, Canal enables fast design space exploration and creation of CGRA interconnects.