Real time QKD Post Processing based on Reconfigurable Hardware Acceleration

TL;DR

This paper presents a high-throughput, reconfigurable FPGA-based framework for quantum key distribution post-processing, supporting multiple protocols with improved speed, security, and interoperability.

Contribution

It introduces a novel FPGA architecture with a Hadoop-based processing model and semi-automated HLS framework for flexible, efficient QKD post-processing.

Findings

Significant performance improvement over existing solutions

Supports multiple QKD protocols with reconfigurable hardware

Compatible with various discrete variable QKD systems

Abstract

Key Distillation is an essential component of every Quantum Key Distribution system because it compensates the inherent transmission errors of quantum channel. However, throughput and interoperability aspects of post-processing engine design often neglected, and exiting solutions are not providing any guarantee. In this paper, we propose multiple protocol support high throughput key distillation framework implemented in a Field Programmable Gate Array (FPGA) using High-Level Synthesis (HLS). The proposed design uses a Hadoop framework with a map-reduce programming model to efficiently process large chunks of raw data across the limited computing resources of an FPGA. We present a novel hardware-efficient integrated post-processing architecture that offer dynamic error correction, a side-channel resistant authentication scheme, and an inbuilt high-speed encryption application, which uses the key for secure communication. We develop a semi automated High level synthesis framework capable of handling different QKD protocols with promising speedup. Overall, the experimental results shows that there is a significant improvement in performance and compatible with any discrete variable QKD systems.