Pixel data real time processing as a next step for HL-LHC upgrades and beyond

TL;DR

This paper explores real-time pixel data processing for HL-LHC upgrades, demonstrating significant trigger performance improvements and high-precision collision point reconstruction using simplified algorithms and look-up tables.

Contribution

It introduces a simplified, real-time pixel tracking method that enhances trigger efficiency and precision, adaptable to various LHC tracking systems and future collider upgrades.

Findings

Rate reduction up to a factor of 20 with >95% efficiency

High-precision collision point reconstruction (20 μm)

Method adaptable to other detectors and future colliders

Abstract

The experiments at LHC are implementing novel and challenging detector upgrades for the High Luminosity LHC, among which the tracking systems. This paper reports on performance studies, illustrated by an electron trigger, using a simplified pixel tracker. To achieve a real-time trigger (e.g. processing HL-LHC collision events at 40 MHz), simple algorithms are developed for reconstructing pixel-based tracks and track isolation, utilizing look-up tables based on pixel detector information. Significant gains in electron trigger performance are seen when pixel detector information is included. In particular, a rate reduction up to a factor of 20 is obtained with a signal selection efficiency of more than 95\% over the whole $\eta$ coverage of this detector. Furthermore, it reconstructs p-p collision points in the beam axis (z) direction, with a high precision of 20 $\mu$m resolution in the very central region ($|\eta| < 0.8$), and, up to 380 $\mu$m in the forward region (2.7 $< |\eta| <$ 3.0). This study as well as the results can easily be adapted to the muon case and to the different tracking systems at LHC and other machines beyond the HL-LHC. The feasibility of such real-time processing of the pixel information is mainly constrained by the Level-1 trigger latency of the experiment. How this might be overcome by the Front-End ASIC design, new processors, and embedded Artificial Intelligence algorithms is briefly tackled as well.