Profile-Guided Parallel Task Extraction and Execution for Domain Specific Heterogeneous SoC

TL;DR

This paper presents a methodology that automatically transforms C/C++ applications into parallel tasks for heterogeneous SoCs using dynamic profiling, enabling efficient execution on multi-core and FPGA-based platforms.

Contribution

It introduces a combined compile-time and runtime system for automatic task extraction and scheduling on heterogeneous SoCs, simplifying parallel application deployment.

Findings

Successfully executed real-life applications with task-level parallelism.

Demonstrated effective scheduling on emulated heterogeneous SoC.

Achieved functional correctness and parallel efficiency.

Abstract

In this study, we introduce a methodology for automatically transforming user applications in the radar and communication domain written in C/C++ based on dynamic profiling to a parallel representation targeted for a heterogeneous SoC. We present our approach for instrumenting the user application binary during the compilation process with barrier synchronization primitives that enable runtime system schedule and execute independent tasks concurrently over the available compute resources. We demonstrate the capabilities of our integrated compile time and runtime flow through task-level parallel and functionally correct execution of real-life applications. We perform validation of our integrated system by executing four distinct applications each carrying various degrees of task level parallelism over the Xeon-based multi-core homogeneous processor. We use the proposed compilation and code transformation methodology to re-target each application for execution on a heterogeneous SoC composed of three ARM cores and one FFT accelerator that is emulated on the Xilinx Zynq UltraScale+ platform. We demonstrate our runtime's ability to process application binary, dispatch independent tasks over the available compute resources of the emulated SoC on the Zynq FPGA based on three different scheduling heuristics. Finally we demonstrate execution of each application individually with task level parallelism on the Zynq FPGA and execution of workload scenarios composed of multiple instances of the same application as well as mixture of two distinct applications to demonstrate ability to realize both application and task level parallel execution. Our integrated approach offers a path forward for application developers to take full advantage of the target SoC without requiring users to become hardware and parallel programming experts.