Parallel decoder for Low Density Parity Check Codes: A MPSoC study

TL;DR

This paper explores a parallel decoding platform for LDPC codes using MPSoC with NoC, demonstrating improved data rate and speedup for a specific LDPC code implementation.

Contribution

It introduces a novel MPSoC-based platform for LDPC decoding utilizing HeMPS and evaluates its performance with the reduced minimum sum algorithm.

Findings

Achieved significant speedup in decoding performance.

Demonstrated the platform's scalability for large LDPC codes.

Validated the approach with simulations on a 252x504 LDPC code.

Abstract

The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Iterative decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252x504 parity matrix is presented