FPGA Implementation of An Event-driven Saliency-based Selective Attention Model

TL;DR

This paper presents an FPGA-based digital architecture for a saliency-driven selective attention model that efficiently processes event-based visual data from a DVS camera, reducing data load for autonomous vision systems.

Contribution

The work introduces a novel FPGA implementation of a saliency-based attention model tailored for event-driven vision sensors, enabling real-time processing with limited hardware resources.

Findings

Efficient FPGA architecture for event-based saliency detection

Real-time processing demonstrated with DVS camera data

Optimized hardware resource utilization

Abstract

Artificial vision systems of autonomous agents face very difficult challenges, as their vision sensors are required to transmit vast amounts of information to the processing stages, and to process it in real-time. One first approach to reduce data transmission is to use event-based vision sensors, whose pixels produce events only when there are changes in the input. However, even for event-based vision, transmission and processing of visual data can be quite onerous. Currently, these challenges are solved by using high-speed communication links and powerful machine vision processing hardware. But if resources are limited, instead of processing all the sensory information in parallel, an effective strategy is to divide the visual field into several small sub-regions, choose the region of highest saliency, process it, and shift serially the focus of attention to regions of decreasing saliency. This strategy, commonly used also by the visual system of many animals, is typically referred to as ``selective attention''. Here we present a digital architecture implementing a saliency-based selective visual attention model for processing asynchronous event-based sensory information received from a DVS. For ease of prototyping, we use a standard digital design flow and map the architecture on an FPGA. We describe the architecture block diagram highlighting the efficient use of the available hardware resources demonstrated through experimental results exploiting a hardware setup where the FPGA interfaced with the DVS camera.