Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays

TL;DR

Cascade is a toolkit that improves the performance and energy efficiency of CGRA applications by automated pipelining and hardware optimizations, achieving significant reductions in delay and energy-delay product across various workloads.

Contribution

The paper introduces Cascade, a comprehensive pipelining toolkit for CGRAs that includes a frequency model, automated pipelining techniques, and hardware optimizations, addressing limitations of existing compilers.

Findings

7-34x lower critical path delays

7-190x lower energy-delay product (EDP) for dense workloads

2-4.4x lower critical path delays and 1.5-4.2x lower EDP for sparse workloads

Abstract

While coarse-grained reconfigurable arrays (CGRAs) have emerged as promising programmable accelerator architectures, pipelining applications running on CGRAs is required to ensure high maximum clock frequencies. Current CGRA compilers either lack pipelining techniques resulting in low performance or perform exhaustive pipelining resulting in high energy and resource consumption. We introduce Cascade, an application pipelining toolkit for CGRAs, including a CGRA application frequency model, automated pipelining techniques for CGRA application compilers that work with both dense and sparse applications, and hardware optimizations for improving application frequency. Cascade enables 7 - 34x lower critical path delays and 7 - 190x lower EDP across a variety of dense image processing and machine learning workloads, and 2 - 4.4x lower critical path delays and 1.5 - 4.2x lower EDP on sparse workloads, compared to a compiler without pipelining.