R & D of prototype iTOF-MRPC at CEE

TL;DR

This paper reports the development and testing of a multi-gap resistive plate chamber prototype with FPGA-based electronics for the CEE experiment, achieving about 30 ps time resolution and analyzing factors affecting its performance.

Contribution

It introduces a 24-gap iTOF-MRPC prototype with FPGA readout and provides simulation-based optimization insights for improving timing resolution.

Findings

Time resolution of approximately 30 ps achieved

Simulation identifies key factors affecting MRPC timing performance

Optimization strategies proposed based on signal transmission analysis

Abstract

The cooling storage ring (CSR) external-target experiment (CEE) is a spectrometer running at the Heavy Ion Research Facility (HIRFL) at Lanzhou. The CEE is the first large-scale nuclear physics experimental device by China to operate in the fixed-target mode with an energy of 1 GeV. The purpose of the CEE is to study the properties of dense nuclear matter. CEE uses a multi-gap resistive plate chamber (MRPC) as its internal time-of-flight (iTOF) detector for the identification of final-state particles. An iTOF-MRPC prototype with 24 gaps was designed to meet the requirements of CEE, and the readout electronics of the prototype use the FPGA-based time digitization technology. Using cosmic ray tests, the time resolution of the iTOF prototype was found to be approximately 30 ps. In order to further understand how to improve the time resolution of MRPC, ANSYS HFSS was used to simulate the signal transmission process in MRPC. The main factors affecting the timing performance of the MRPC and, accordingly, the optimization scheme are presented.