Large Scale Integration of Graphene Transistors for Potential Applications in the Back End of the Line

TL;DR

This paper demonstrates a wafer-scale, CMOS-compatible method for fabricating graphene transistors, enabling large-scale integration and paving the way for future reliability studies and commercial applications.

Contribution

It introduces a scalable, back-end-of-line compatible fabrication process for graphene transistors, advancing towards industrial integration.

Findings

Carrier mobilities reach several hundred cm^2V^{-1}s^{-1}

Devices exhibit current saturation similar to exfoliated graphene

Performance currently below mechanically exfoliated graphene devices

Abstract

A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm$^2$V$^{-1}$s$^{-1}$. Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introducing graphene into wafer scale process lines.