Design and Performance Analysis of Hardware Realization of 3GPP Physical Layer for 5G Cell Search

TL;DR

This paper presents a hardware implementation of 5G cell search, introducing a novel down-sampling detection method that reduces complexity and latency, validated through extensive performance analysis and hardware demonstration.

Contribution

It introduces a 3GPP-compatible hardware design for 5G cell search with a novel down-sampling detection approach, improving efficiency and enabling practical hardware deployment.

Findings

Significant reduction in detection complexity and latency

Successful demonstration on GNU Radio and USRP-FPGA hardware

Validated performance across various SNRs and down-sampling factors

Abstract

5G Cell Search (CS) is the first step for user equipment (UE) to initiate the communication with the 5G node B (gNB) every time it is powered ON. In cellular networks, CS is accomplished via synchronization signals (SS) broadcasted by gNB. 5G 3rd generation partnership project (3GPP) specifications offer a detailed discussion on the SS generation at gNB but a limited understanding of their blind search, and detection is available. Unlike 4G, 5G SS may not be transmitted at the center of carrier frequency and their frequency location is unknown to UE. In this work, we demonstrate the 5G CS by designing 3GPP compatible hardware realization of the physical layer (PHY) of the gNB transmitter and UE receiver. The proposed SS detection explores a novel down-sampling approach resulting in a significant reduction in complexity and latency. Via detailed performance analysis, we analyze the functional correctness, computational complexity, and latency of the proposed approach for different word lengths, signal-to-noise ratio (SNR), and down-sampling factors. We demonstrate the complete CS functionality on GNU Radio-based RFNoC framework and USRP-FPGA platform. The 3GPP compatibility and demonstration on hardware strengthen the commercial significance of the proposed work.