Fully Digital Second-order Level-crossing Sampling ADC for Data Saving in Sensing Sparse Signals

TL;DR

This paper introduces a fully integrated second-order level-crossing sampling ADC that efficiently compresses data and reduces power consumption for sensing sparse signals, especially in low-power sensor applications.

Contribution

It proposes a novel second-order level-crossing sampling method with sloped levels, implemented by modifying digital control logic of a SAR ADC, enabling data and power savings.

Findings

Achieves 30% data savings compared to conventional SAR ADCs.

Attains a compression factor of 6.17 for ECG signal tracking.

Demonstrates effective real-time data compression and feature extraction.

Abstract

This paper presents a fully integrated second-order level-crossing sampling data converter for real-time data compression and feature extraction. Compared with level-sampling ADCs which sample at fixed voltage levels, the proposed circuits updates tracking thresholds using linear extrapolation, which forms a second-order level-crossing sampling ADC that has sloped sampling levels. The computing is done digitally and is implemented by modifying the digital control logic of a conventional SAR ADC. The system selects only the turning points in the input waveform for quantization. The output of the proposed data converter consists of both the digital value of the selected sampling points and the timestamp between the selected sampling points. The main advantages are data savings and power savings for the data converter and the following digital signal processing or communication circuits, which are ideal for low-power sensors. The test chip was fabricated using a 180nm CMOS process. The proposed ADC saves 30% compared to a conventional SAR ADC and achieves a compression factor of 6.17 for tracking ECG signals.