Highly optimized quantum circuits synthesized via data-flow engines

TL;DR

This paper presents a novel FPGA-based data-flow engine approach to optimize quantum circuit synthesis, significantly reducing circuit depth while maintaining high fidelity, thus enhancing quantum program efficiency on noisy hardware.

Contribution

It introduces a DFE-based quantum circuit synthesizer that scales to 9-qubit programs, achieving substantial depth reduction and high fidelity compared to existing methods.

Findings

Circuit depth reduced by 97% on average

Fidelity maintained close to unity (~10^{-4})

Scales up to 9-qubit quantum programs

Abstract

The formulation of quantum programs in terms of the fewest number of gate operations is crucial to retrieve meaningful results from the noisy quantum processors accessible these days. In this work, we demonstrate a use-case for Field Programmable Gate Array (FPGA) based data-flow engines (DFEs) to scale up variational quantum compilers to synthesize circuits up to $9$-qubit programs.This gate decomposer utilizes a newly developed DFE quantum computer simulator that is designed to simulate arbitrary quantum circuit consisting of single qubit rotations and controlled two-qubit gates on FPGA chips. In our benchmark with the QISKIT package, the depth of the circuits produced by the SQUANDER package (with the DFE accelerator support) were less by $97\%$ on average, while the fidelity of the circuits was still close to unity up to an error of $\sim10^{-4}$.