A Variable Node Design with Check Node Aware Quantization Leveraging 2-Bit LDPC Decoding

TL;DR

This paper introduces a check node aware variable node design for LDPC decoding that maximizes mutual information preservation, leading to improved performance with coarse quantization and more efficient hardware implementation.

Contribution

It proposes a novel variable node update optimized for mutual information, enhancing coarse quantized LDPC decoding performance and hardware efficiency.

Findings

Achieves up to 0.2 dB performance gain with 2- or 3-bit messages.

Enables hardware reduction by 78% and fourfold delay decrease.

Validates effectiveness through simulations on regular LDPC codes.

Abstract

For improving coarsely quantized decoding of LDPC codes, we propose a check node aware design of the variable node update. In contrast to previous works, we optimize the variable node to explicitly maximize the mutual information preserved in the check-to-variable instead of the variable-to-check node messages. The extended optimization leads to a significantly different solution for the compression operation at the variable node. Simulation results for regular LDPC codes confirm that the check node aware design, especially for very coarse quantization with 2- or 3-bit messages, achieves performance gains of up to 0.2 dB - without additional hardware costs. We also show that the 2-bit message resolution enables a very efficient implementation of the check node update, which requires only 2/9 of the 3-bit check node's transistor count and reduces the signal propagation delay by a factor of 4.