High-Level Synthesis for Packet-Processing Pipelines

TL;DR

This paper introduces a high-level synthesis approach for compiling high-speed packet-processing pipelines, improving resource utilization and compilation speed by decomposing the problem into modular phases.

Contribution

It applies HLS techniques to pipeline compilation, proposing a three-phase compiler that enhances resource efficiency and handles complex programs beyond current capabilities.

Findings

Handles programs that existing compilers cannot run

Generates code faster than existing compilers

Uses fewer pipeline resources

Abstract

Compiling high-level programs to target high-speed packet-processing pipelines is a challenging combinatorial optimization problem. The compiler must configure the pipeline's resources to match the high-level semantics of the program, while packing all of the program's computation into the pipeline's limited resources. State of the art approaches tackle individual aspects of this problem. Yet, they miss opportunities to efficiently produce globally high-quality outcomes. We argue that High-Level Synthesis (HLS), previously applied to ASIC/FPGA design, is the right framework to decompose the compilation problem for pipelines into smaller pieces with modular solutions. We design an HLS-based compiler that works in three phases. Transformation rewrites programs to use more abundant pipeline resources, avoiding scarce ones. Synthesis breaks complex transactional code into configurations of pipelined compute units. Allocation maps the program's compute and memory to the hardware resources. We prototype these ideas in a compiler, CaT, which targets the Tofino pipeline and a cycle-accurate simulator of a Verilog hardware model of an RMT pipeline. CaT can handle programs that existing compilers cannot currently run on pipelines, generating code faster than existing compilers, while using fewer pipeline resources.